1. Field of the Invention
This invention relates to a method of fabricating semiconductors, and more particularly to a method of fabricating wells.
2. Description of Related Art
The application of the data treatment at present is similar to the typical utilization in microprocessor and digital signal processor, which combine memory cell arrays and high-speed logic circuits on the same chip. For example, a high speed is used to store data into an integrated circuit device, such as a logic circuit, which has a DRAM cell array. This embedded DRAM has large benefits for the integrated circuit, which includes a logic circuit capable of processing large amount of data, such as graphic processor. For the process to combine the high-speed logic circuit and embedded DRAM on the same chip, it is necessary to form the logic circuit and memory cell on the chip.
For the conventional embedded DRAM of the integrated circuit, both the MOS transistor which is used for the DRAM and the MOS transistor which is used for the logic device are formed on the same chip. It has several advantages, such as improvement of the yield, and reducing of cycle time and manufacturing cost.
FIG. 1A to FIG. 1D are cross-sectional views showing a conventional process of fabricating wells. Referring to FIG. 1A, a substrate 10 is provided. The substrate 10 is doped with p-type ions, that is a p-type substrate, is provided, the dosage of p-type ions is about 5E16/cm.sup.3. Then, a mask 12 is formed to cover part of the substrate 10 and expose another part of the substrate 10. Thereafter, an n-well 14 is formed in the exposed substrate 10 by doping n-type ions, which have a dosage of about 1E17/cm.sup.3, into the exposed substrate 10.
Referring to FIG. 1B, the mask 12 is removed after the n-well 14 is formed. Then, a mask 16 is formed to cover the surface of the n-well 14 and expose another part of the substrate 10. Thereafter, a p-well 18 is formed in the exposed substrate 10 by doping p-type ions which have a dosage of about 1E17/cm.sup.3 into the exposed substrate 10.
Referring to FIG. 1C, the mask 16 is removed after the p-well 18 is formed. A mask 20 is formed to cover substrate 10 and partially expose the surface of the n-well 14. Then, a p-well 22, which is a triple well, is formed by doping p-type ions, which have a dosage of about 3E17/cm.sup.3, into the exposed part of the n-well 14. P-well 22 is formed in the n-well 14 and the p-well 22 is shallow than the n-well 14. That is, three surfaces of the p-well 22 are surrounded by the n-well 14 and one surface of the p-well 22 is exposed.
Referring to FIG. 1D, the mask 20 is removed after the p-well 22 is formed. Then the follow-up process is performed to complete the manufacture of the DRAM above the n-well 14 and the n-channel device above p-well 18. The DRAM and n-channel device are not shown to simplify the figures.
In the conventional method as described above, it is necessary to implant high dosage p-type ions into the n-well 14 to form the triple well. Therefore, the dosage of the triple well is higher than that of the n-well 14. When the DRAM is completed in subsequent processes, the DRAM's refresh time is shortened.